1. Field of the Invention
This invention relates to a silicon carbide semiconductor device, especially to an insulated gate type field effect transistor such as a high-power vertical MOSFET, and a method of manufacturing the same.
2. Description of the Related Art
The applicant of the present invention proposes in pending U.S. patent application Ser. No. 09/035,204 a planar-type MOSFET for improving channel mobility and for lowering ON-resistance. Referring to FIG. 1, the planar-type MOSFET includes an n.sup.+ type semiconductor substrate 1 made of silicon carbide (SiC) and having a main surface 1a and a back surface 1b on a side opposite to the main surface 1a. An n.sup.- type epitaxial layer (herebelow, referred to as n.sup.- epi-layer) 2 is formed on the main surface 1a of the n.sup.+ type semiconductor substrate 1 to have a dopant (impurity) concentration lower than that of the substrate 1. In specific surface regions of the n.sup.- type epi-layer 2, p.sup.- type base regions 3a, 3b are formed at a specific depth to be separated from one another. In specific surface regions of the p.sup.- type base regions 3a, 3b, n.sup.+ type source regions 4a, 4b are formed at a depth shallower than that of the base regions 3a, 3b.
An n.sup.- type SiC layer 5 is extended in surface regions of the n.sup.- type epi-layer 2 and the p.sup.- type base regions 3a, 3b, between the n.sup.+ type source regions 4a, 4b, thereby connecting the source regions 4a, 4b and the n.sup.- type epi-layer 2 via the surface regions of the p.sup.- type base regions 3a, 3b. The n.sup.- type SiC layer 5 is formed through epitaxial growth to have 4H, 6H, or 3C type crystal structure. When the device is operated, the n.sup.- type SiC layer 5 functions as a channel formation layer. Herebelow, the n.sup.- type SiC layer 5 is referred to as a surface channel layer. The surface channel layer 5 is doped with nitrogen (N) as dopant, with a low dopant concentration, for example, in a range of 1.times.10.sup.15 cm.sup.-3 to 1.times.10.sup.17 cm.sup.-3 which is generally less than the dopant concentrations of the n.sup.- type epi-layer 2 and the p.sup.- type base regions 3a, 3b. Accordingly, low ON-resistance is realized.
A gate oxide film 7 is formed from silicon dioxide (SiO.sub.2) on the surface channel layer 5 and the n.sup.+ type source regions 4a, 4b, and a gate electrode 8 is further formed on the gate oxide film 7. The gate electrode 8 is covered with an insulation film 9. The insulation film 9 is made of LTO (Low Temperature Oxide). A source electrode 10 is formed on the insulation film 9 to contact the n.sup.+ type source regions 4a, 4b and p.sup.- type base regions 3a, 3b. A drain electrode layer 11 is formed on the back surface 1b of the n.sup.+ type semiconductor substrate 1.
The thus constructed planar-type MOSFET operates at an accumulation mode in which a channel region is induced without inverting the conductive type of the channel formation layer. Therefore, the channel mobility can be increased and the ON-resistance can be lowered as compared with those of an inversion mode MOSFET which is accompanied by inversion of the conductive type to form a channel.
The inventors of the present invention manufactured the planar-type power MOSFET described above, and examined the gate oxide film 7 of the MOSFET by means of light illumination C-V measurement. The resultant C-V characteristic is shown in FIG. 2. As a result, it was founded that the C-V characteristic was largely varied by illumination, and after that it did not recover immediately. That is, it was founded that the C-V characteristic had the so-called hysteresis characteristic. In addition, a flat-band voltage was shifted to a positive side. This implies that electron traps arose.
This phenomenon indicates that carrier traps exist in the gate oxide film or at an interface between the gate oxide film and the surface channel layer 5 (SiO.sub.2 /SiC interface), and can cause not only instability of FET characteristics but deterioration in reliability to the gate oxide film 7.